### Content

- 1: Start .
- 2: Documentation .
- 3: Related Publications .
- 4: Terms of Use .
- 5: Licensing Options for Companies .

# Documentation

## Input Signal

In the current implementation each individual modulator is tested via single sine wave inputs at 8 different amplitudes but with the same input frequency. These amplitudes are linearly spaced between selectable minimum and maximum values. The frequency can be set in percent of the inband.

Amplitude | Input amplitude min. and max. |

Frequency | Input frequency |

### Amplitude

For the imput amplitude a certain range can be set between Min. = [0.001;Max) and Max. = (Min;2].

### Frequency

The normalized input frequency can be set between [0.01;1] in f/fs.

## Hints for the optimization

### Amplitudes

The covered range of the amplitudes can be utilized in order to aim for a certain maximum stable amplitude (MSA). E.g., when selecting 0.7 for Min and 0.8 for Max, only modulators which are stable in that range are evaluated as good. However, the tougher the constraints the higher the chance that no modulator can be found at all.

### Frequency

Inserting a frequency lower than 1/3 times the inband will include the third harmonic produced by the quantizer. Thereby, the more robust modulators are favoured.

## Examples

### Amplitudes

Selecting for the minimum and maximum amplitude values:

- Min = 0.3
- Max = 1.0

results in the test amplitudes:

Test signal # | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |

Test amplitude | 0.3 | 0.4 | 0.5 | 0.6 | 0.7 | 0.8 | 0.9 | 1.0 |

### Frequency

Selecting a frequency of

- Frequency = 0.3

results in a tone right in the middle of the band of interest at (3/10) * fs/(2*OSR). Increasing or decreasing the value shifts the signal peak indicated by the arrows in the following figure.

top## Integrators

The current implementation allows for selecting one out of three integrator types. The designer can choose between an ideal model, a model that incorporates an operational amplifier (OA) with one dominant pole, and a model with a dominant pole in the OA and proportional path. In case of a 1-pole model, DC gain and gain-band-widths (GBW) can either be fixed prior to the optimization or optimized themselves. The proportional paths considered as a modulator coefficient and can also either be fixed or optimized. Additionally, optimization goals for the output swings can be set.

Model type | Ideal | Ideal integrator model. |

1-Pole | Integrator model with dominant pole in the OA. | |

1-Pole + PI | Integrator model with dominant pole in the OA and proportional path. | |

Dynamics | Optimize for a defined minimum and maximum integrator output swing. | |

DC gain | minimize | Allow the genetic algorithm to minimize this value. |

fixed | Fixed to value during optimization. | |

GBW | minimize | Allow the genetic algorithm to minimize this value. |

fixed | Fixed to value during optimization. | |

Prop. path | optimize | Optimize coefficient value. |

fixed | Fix coefficient to a certain value. |

### Model type

#### Ideal

Ideal integrator means, the integrator is ideal by all matters. There are no limitations in DC gain, GWB, etc. Each ideal integrator represents one state in the state-space model of the overal modulator model, which is used for optimization. A high-level model for multiple inputs is shown in the figure below on the left side and a low level model is shown on the right. Here, the low-level model of the OA has a transfer characteristic of A(s)= infinity.

#### 1-Pole

In the 1-pole integrator model, the dominant pole of the OA is accounted for in order to investigate the most dominant non-ideal behavior. By this pole, finite DC gain and finite GBW can be modeled. As shown below, each 1-pole integrator represents two states in the state-space model of the overal modulator model, which is used for optimization, obviously leading to smaller simulation throughputs than the ideal models. During the optimization gain errors due to multiple resistive inputs is accounted for automatically.

#### 1-Pole + PI

As in the 1-pole integrator model without proportional path, the dominant pole of the OA is accounted for in order to investigate the most dominant non-ideal behavior. By this pole, finite DC gain and finite GBW can be modeled. As shown below, also each 1-pole integrator with proportional path represents two states in the state-space model of the overal modulator model, which is used for optimization, obviously leading to smaller simulation throughputs than the ideal models. During the optimization gain errors due to multiple resistive inputs is accounted for automatically. In the current implementation, the model is implemented as shown below. Therefore, possible resonators feed back not only the integrated but also the proportionally scaled signal.

### Dynamics

Defines and optimization goal for the output swing of the integrator. Modulators with swings lower than the Min. or higher then the Max. value are rated worse than ones within this boundaries.

### DC gain

#### Minimize

Allow the genetic algorithm to change the DC gain value in order to find a minimal acceptable value. This option enables the choice of Min. and Max. boundaries for a defined, allowed range. ATTENTION! Low DC gain values will result in poor linearity, which is not investigated during the optimization!

#### Fixed

Fixes the DC gain to a defined value during optimization. This option enables to choose the defined value. Possible values are: x=[10;100000] on an absolute scale.

### GBW

#### Minimize

Allow the genetic algorithm to change the GBW value in order to find a minimal acceptable value. This option enables the choice of Min. and Max. boundaries for a defined, allowed range.

#### Fixed

Fixes the GBW to a defined value during optimization. This option enables to choose the defined value. Possible values are: x=[0.1;10] times the sampling frequency fs. Higher values than 10 times fs are considered as ideal and, thus, not supported.

### Proportional Path

#### Optimize

Optimize enables the genetic algorithm to change the value of this coefficient in order to find a better modulator. This option enables the choice of Min. and Max. boundaries for a defined, allowed range.

#### Fixed

Fixes the coefficient to a defined value during optimization. This option enables to choose the defined value. Possible values are: x=[0.00001;100].

top## High-Level Coefficients

In the high-level block diagram the modulator coefficients are ideal signal scaling blocks. Nevertheless, in order to account also for low-level behavior, already some additional options are implemented. E.g., the designer can choose between resistive or capacitive coupling of the feed forward paths, which effects the integrator output swings and the integrator gain error.

For the optimization all coefficients of the modulator can be individualized seperately. The designer can set fixed coefficient values or optimize the values with or without previously set upper and lower boundaries as optimization goals. The coefficient blocks currently have the following parameters:

activate/deactivate | Enable/disable path during optimization. | |

Type | resistive | Path realization via resistor. |

capacitive | Path realization via capacitor. | |

Value | optimize | Optimize coefficient value. |

fixed | Fix coefficient to a certain value. | |

same as a1 | (b1=a1) during optimization. |

### Activate/Deactivate

This button adds or removes the coefficient from the block diagram. It is available for all coefficients but a1, b1 and cx with x=[1,2,.., order+1], since these are considered as mandatory.

### Type

There are two options for the coupling of the coefficient with the integrator.

#### Resistive

Resistive input means the input to the integrator is formed by a resistor as shown below. This path affects the integrator gain, which is accounted for automatically.

#### Capacitive

Capacitive input means the input to the integrator is formed by a capacitor as shown below. In this case, a high-level path according to the model in the main window is formed across an integrator even though in the low-level domain the signal is forwarded by the proportional behavior through the integrator. This path does not affect the integrator gain but certainly the integrator swing. The option "capacitive" is only available for paths, which overlap an non-ideal, non-proportional integrator, i.e., an integrator modeled by a 1-pole model without proportional path. Capacitive paths with ideal models can be investigated by inserting appropriate ideal paths. Capacitive paths across integrators with proportional paths is not possible.

### Value

#### Optimize

The "optimize" option enables the genetic algorithm to change the value of this coefficient in order to find a better modulator. This option enables the choice of Min and Max boundaries for a defined range, which is allowed for the coefficient.

#### Fixed

It is possible to set the coefficient to a defined value during optimization. Possible values are: x=[0.00001;100].

#### Same as a1

Fix the coefficient b1 to the same value as a1 during optimization. This option is set by default. Modulators, which do not have any other inputs to the first summing node than the paths through a1 and b1, exhibit an STF of 0 dBFS for low frequencies, if b1 equals a1.

top## Internal Quantizer

The quantizer is considered as an ideal element, while dithering is possible.

Quantizer levels | Number of quantizer levels |

Dithering | Add random noise onto the quantizer input |

Dynamics | Optimize for a defined quantizer input swing |

### Quantizer Levels

Defines the number of levels in the quantizer. An even number results in a mid-rise, while an odd number results in a mid-thread quantizer characteristic. Possible values are: x=[2;64].

### Dithering

Adds noise onto the quantizer input during each sampling instant. The noise is uniformly distributed and the interval is defined by +/- the chosen value. Possible values for dithering are: x=[0;10], while the value x is normalized to one quantizer stepwidth and thus scales down automatically with increasing number of quantizer levels.

### Dynamics

Defines and optimization goal for the input swing of the quantizer. Modulators with swings lower than the Min. or higher then the Max. value are rated worse than ones within this boundaries.

top## D/A Converter

The D/A converters of the block diagram form the feedback paths and can account for some low-level behavior. The designer can choose between resistive,current source and for the last DAC capacitive coupling of the feedback paths, which effects the integrator output swings and the integrator gain error.

For the optimization all D/A converters of the modulator can be individualized seperately. The designer can set fixed coefficient values or optimize the values with or without previously set upper and lower boundaries as optimization goals. Further, the output waveform and a local delay can be set. The D/A converters blocks currently have the following parameters:

activate/deactivate | Enable/disable path during optimization. | |

Type | resistive | Path realization via resistor. |

capacitive | Path realization via capacitor. | |

current source | Path realization via current source. | |

Value | optimize | Optimize coefficient value. |

fixed | Fix coefficient to a certain value. | |

D/A settings | path | Path for last DAC |

local ELD | Local delay of the signal | |

waveform | Output waveform (NRZ, RZ, RCOS, EXP) |

### Activate/Deactivate

This button adds or removes the D/A converter from the block diagram. It is available for all coefficients but a1, b1 and cx with x=[1,2,.., order+1], since these are considered as mandatory.

### Type

There are up to three options for the coupling of the D/A converter with the integrator. The last D/A converter has more options, as its signal is added to the output of the last integrator.

#### Resistive

Resistive input means the input is formed by a resistor as seen below. This path affects the integrator gain, which is accounted for automatically.

#### Capacitive

Capacitive input is only available for the last D/A converter. It means that the path is formed by a capacitor to the last integrator as seen below. In the block diagram this path is represented by a summation of the signals after the integrator. Therefore the "path" option of the D/A converter has to be set "to adder" (see path). In this case, a high-level path according to the model in the main window is formed across an integrator even though in the low-level domain the signal is forwarded by the proportional behavior through the integrator. This path does not affect the integrator gain but certainly the integrator swing. Furthermore, for the last integrator the 1-pole model without proportional path has to be chosen. The capacitive path with the ideal model can be investigated by inserting the appropriate ideal path.

#### Current Source

Current source means the input is formed by a current source. The integrator gain is not affected.

### Value

#### Optimize

The "optimize" option enables the genetic algorithm to change the value of this coefficient in order to find a better modulator. This option enables the choice of Min and Max boundaries for a defined range, which is allowed for the coefficient.

#### Fixed

It is possible to set the coefficient to a defined value during optimization. Possible values are: x=[0.00001;100].

### D/A settings

#### Path

For ELD compensation the path of the last DAC can be changed either to the last integrator or the adder.

#### Local ELD

The value for the local excess-loop-delay can be chosen to ELD = [0;1]. In contrast to the global ELD it is an individual value for each DAC. Here, the value is normalized to the duration of one sampling clock cycle Ts = 1/fs.

#### Waveform

The DAC output waveform can be chosen individually for each feedback DAC. Non-return-to-zero (NRZ), return-to-zero (RZ), raised cosine (RCOS) and exponential decay (EXP) are available.

top## Global Excess-Loop-Delay

The ELD block adds an global excess-loop-delay to all feedback paths.

Excess-loop-delay | Combined delay of the quantizer and DAC. |

### Excess-loop-delay

The value for the ELD can be chosen to ELD = [0;1]. Here, the value is normalized to the duration of one sampling clock cycle Ts = 1/fs.

top